
#TOP_NAME = top
#TOP_NAME = ysyx_20220337_IFU
#TOP_NAME = ysyx_20220337_IDU
#TOP_NAME = ysyx_20220337_Decode
TOP_NAME = ysyx_20220337_CPU

#FILE_NAME = file.f
#FILE_NAME = ysyx_20220337_IFU.f
#FILE_NAME = ysyx_20220337_IDU.f
FILE_NAME = ysyx_20220337_CPU.f

all:    clean sim compile
	@echo "Write this Makefile by your self."
	
clean:  
	rm -rf obj_dir
	rm -f wave.vcd

	

sim:
	$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
	@echo "Write this Makefile by your self."
	#verilator -Wno-fatal vsrc/our_OnOff.v csrc/sim_main.c --top-module ${TOP_NAME} --cc --trace --exe
	verilator -Wno-fatal -f ${FILE_NAME} --top-module ${TOP_NAME} --cc --trace --exe
compile:
	#make -C obj_dir -f Vtop.mk Vtop
	make -C obj_dir -f V${TOP_NAME}.mk V${TOP_NAME}
	./obj_dir/V${TOP_NAME}
	
wave:
	gtkwave wave.vcd
        
include ../Makefile
